JP-A-2001-175702 (Patent Document 1) discloses a method of designing a circuit in which a bypass capacitor is equipped to an integrated circuit (IC). According to this circuit designing method, the capacitance of the bypass capacitor and the arrangement location thereof (the position at which the bypass capacitor is disposed) are preset and then circuit values, such as noise current, are estimated based on an impedance-frequency characteristic of the capacitor current path. This operation is repeated for optimizing the circuit design.
When the IC is mounted on a printed circuit board, a bypass capacitor (hereinafter referred to as a “capacitor”) is equipped between the power supply terminals of the IC in order to reduce the introduction of external noise through a power supply path into the IC and noise externally output from the IC through the power supply path.
FIG. 5 shows a related art noise analyzing model for designing a capacitor mount circuit. In FIG. 5, Zcap represents the impedance of a capacitor 4 connected between the power supply terminals 2, 3 of the IC 1, Zpcb represents the impedance of an external circuit 7 connected between the power supply paths 5, 6 when viewed from the capacitor 4 to the opposite side to IC 1, Zptnv1 represents the impedance of a portion of the power supply path 5 extending from the power supply terminal 2 to the capacitor 4, Zptng1 represents the impedance of a portion of the power supply path 6 extending from the power supply terminal 3 of the IC 1 to the capacitor 4, Zptnv2 represents the impedance of a portion of the power supply path 5 extending from the capacitor 4 to the external circuit 7, and zptng2 represents the impedance of a portion of the power supply path 6 extending from the capacitor 4 to the external circuit 7.
When calculation is carried out by using this noise analysis, it is concluded that if the impedance of a current path P1 extending from the power supply terminal 2 of the IC 1 through the power supply path 5, the capacitor 4, and the power supply path 6 to the power supply terminal 3 of the IC 1 is lowered relative to the impedance of a current path P2 extending from one end terminal of the capacitor 4 through the power supply path 5, the external circuit 7 and the power supply path 6 and returning to the other terminal of the capacitor 4. Also, noise current flowing out from IC 1 to the external circuit 7 can be reduced. More particularly, according to the related art noise analysis model, it is concluded that the noise current can be reduced if the capacitor 4 is disposed in maximum proximity to IC 1.
However, when the device is actually mounted on a printed circuit board and the noise characteristic is measured, a reduction in noise current is not necessarily achieved by disposing the capacitor 4 in the vicinity of the IC 1. This is because the related art noise analysis model shown in FIG. 5 does not accurately represent the actual circuit. Accordingly, mount circuit designers have been required to repeatedly experiment (perform plural trials) with the capacitance values of the capacitor 4 and the arrangement locations thereof and make repeated estimations until the optimum estimation result is achieved. This must be done despite the calculation result described above.